This invention relates to digital-to-analog converter systems (DAC's) and more particular to apparatus to enhance the effective bandwidth of bandwidth limited DAC's.
The invention will be described in the environment of digital video signal processing systems, but will be recognized to have more general applicability. Recent advances in integrated circuit design and processing have made possible the realization of TV receivers in which the video signal is processed digitally. Typically, baseband composite video signal at the tuner is sampled at four times the color subcarrier (e.g. 14.32 MHz for NTSC systems) and converted to binary format. The binary representation of the video signal is processed in arithmetic devices to ultimately develop R, G, B color signals for driving an image display tube. Input signals to currently available display tubes are required to be analog signals, thus, at some point the processed binary signals must be converted back to analog form. This operation is performed by DAC's which operate at the sample rate of 14.3 MHz.
To enhance the image quality of certain of these digital receivers it is desired to display twice the number of horizontal image lines normally displayed in a field while maintaining the number of fields displayed per second constant. This requirement doubles the rate of samples which must be processed by the DAC's. The sample rate is increased to approximately 28.6 MHz for NTSC signals (and approximately 35 MHz for PAL signals).
DAC's exist, in for example bipolar technology, capable of processing signals at these higher rates. However, they are expensive and dissipate relatively large amounts of power. The majority of the digital video signal processing elements in the digital receiver tend to be insulated gate field effect or MOS devices. MOS DAC's are presently capable of processing the binary video samples at the lower rates, e.g. 14 MHz, but not at the doubled rate. Yet it is desirable, for power dissipation and integrated circuit interfacing reasons, to use MOS DAC's.
If you have devices that operate at one-half the desired rate, one solution is to time division multiplex two such devices operating in parallel. However, time division multiplexing the output signals of two DAC's at a 28 MHz rate is not easily accomplished. Significant switching signals are coupled into the multiplexed analog signal and the DAC's must have matched DC parameters not to introduce switching rate harmonics.
It is an object of the present invention to operate two DAC's in parallel at half the input sample rate, and to combine the output signals from the DAC's without multiplexing, thus, eliminating switch transient contamination and DC offset problems.